• This is the first post of a larger project, in fact, the largest of my projects so far: To build a 16bit CPU from 74HC chips. Now you may ask “Why?”, and then I might reply “Because (I think) I can!”. I just like circuits which are relatively simple in each part but rather complex as a whole. A CPU is the perfect example for a structure which is comprised of many simple parts which have to work in perfect synchronicity.

    This post is intended to give an overview over the main features and specs which will define the structure of the CPU. The implementation of each unit will be detailed in future posts.

    The following attributes are defining for the overall structure of the CPU and were either determined in advance or during the planning phase:

    • 16bit data bus
    • 16bit address bus
    • Four 16bit general purpose registers
    • Four 16bit special purpose registers
    • Each general purpose register can be accessed bytewise
    • 16bit program counter
    • Internal structure microcode controlled
    • Max. 127 microcode steps per instruction
    • Fully static design down to 0Hz
    • 16bit instructions (8bit Opcode, 8bit Parameters)
    • 8bit flag register
    • One external interrupt
    • 256 interrupt vectors
    • 64bit wide microcode instructions

    The microcode approach was chosen because of its simplicity and flexibility over a combinatorial logic design, despite being slower. If an instruction is to be added, changed or removed, this is simply a matter of reprogramming the microcode storage instead of rewiring a whole lot of chips. In the circuit, the microcode is just a number of cascaded memory chips (SRAM or EEPROM) with each data output pin wired to a control pin of one part of the CPU. Each instruction walks through a specified number of addresses, which in turn output a previously programmed sequence of data bits that control each part of the CPU to be active at precisely the right moment. For example, one data bit could be wired to the output enable of a register A and another data bit to the load enable of a different register B. If those to bits were to be active in the same clock cycle, the data from register A would by copied to register B.

    After planning all parts of the CPU with all their control inputs the number of necessary microcode bits added up to 62. The nearest multiple of 8 being 64, I used eight EEPROMs with an 8bit data interface and 16bit address bus. Their outputs will control and coordinate all other units of the CPU, each of which will get its own post:

    Overview of Internal Structure

    Overview of Internal Structure

    • Microcode storage and microcode counter with jump conditions
    • General Purpose Registers with read and write logic
    • Special Purpose Registers with read, write and counter logic
    • 16-bit ALU and 16-bit Shifter with flag calculation, input and output control
    • Flags register with read, write and set logic
    • Program counter
    • External bus interface

    At the time of writing this post, the design has been almost completed, so the specifications are unlikely to change significantly.

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